An efficient implementation of GLCM algorithm in FPGA

M a Ben Atitallah , Rostom Kachouri (1) , H. Mnif (2) , M Kammoun

1 LIGM - Laboratoire d'Informatique Gaspard-Monge
2 ENET'COM - École Nationale d'Électronique et des Télécommunications de Sfax

This paper presents hardware (HW) architecture for fast parallel computation of Gray Level Co-occurrence Matrix (GLCM) in high throughput image analysis applications. GLCM has proven to be a powerful basis for use in texture classification. Various textural parameters calculated from the GLCM help understand the details about the overall image content. However, the calculation of GLCM is very computationally intensive. In this paper, an FPGA accelerator for fast calculation of GLCM is designed and implemented. We propose an FPGA-based architecture for parallel computation of symmetric co-occurrence matrices. This architecture was implemented on a Xilinx Zedboard and Virtex 5 FPGAs using Vivado HLS. The performance is then compared against other implementations. The validation results show an optimization on the order of 33% in latency number by contribution to the literature implementation.

Mots clés: Image analysis applications; Symmetric Co-occurrence matrix (GLCM); Parallel computation; Haralick's texture feature; Hardware Implementation; FPGA; Vivado HLS; Optimization; Latency number

Domaines: Informatique [cs]; Architectures Matérielles [cs.AR]

M a Ben Atitallah, Rostom Kachouri, H. Mnif, M Kammoun. An efficient implementation of GLCM algorithm in FPGA. IEEE International Conference on Internet of Things, Embedded Systems and Communications (IINTEC), Dec 2018, Hammamet, Tunisia. ⟨10.1109/IINTEC.2018.8695275⟩. ⟨hal-01955368⟩