Latency and power optimization in AAA methodology for integrated circuits

Abstract : Field Programmable Gate Arrays (FPGA) are flexible, so they are commonly used in many high speed applications. However, power constraints are the most important limiting factors while implementing high speed adaptable applications. This work addresses the optimization of the execution time and power consumption. We propose a new design methodology by extending Algorithm-Architecture-Adequacy (AAA) methodology. It provides an implementation which meets real time constraints and allows the designer to optimize power consumption or material resources. The extension has been implemented in AAA software tool called Synchronized Distributed Executive for Integrated Circuits (SynDEx-IC). The experimental results show that the mentioned software tool provides an architecture that consumes less power among the explored ones, which the average power is reduced by 15.75%.
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Conference papers
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https://hal-upec-upem.archives-ouvertes.fr/hal-01192801
Contributor : Thierry Grandpierre <>
Submitted on : Thursday, September 3, 2015 - 3:30:28 PM
Last modification on : Tuesday, February 5, 2019 - 9:14:02 AM

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Yareb Eloumi, Mohamed Akil, Thierry Grandpierre, Mohamed Hédi Bedoui. Latency and power optimization in AAA methodology for integrated circuits. ICECS 2010, IEEE, Dec 2010, Athens, Greece. pp.639-642, ⟨10.1109/ICECS.2010.5724593⟩. ⟨hal-01192801⟩

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