Abstract : The design of a 500 MHz oscillator in a 65 nm CMOS process using a 2 GHz bulk acoustic wave (BAW) resonator is presented. A digital frequency control is implemented using a switched capacitor bank in parallel to the resonator. The tuning range is up to 500 kHz with a minimum step of 200 Hz. The oscillator core uses a differential topology and is designed for low phase noise (2128 dBc/Hz at 100 kHz offset) at low power consumption (0.9 mW). It is followed by a low-noise divider, which provides a 500 MHz output with a phase noise of 2139 dBc/Hz at 100 kHz offset from the carrier.