A 2GHz 65nm CMOS digitally-tuned BAW oscillator

Pierre Guillot; Pascal Philippe; Corinne Berland; Jean-François Bercher

doi:10.1109/ICECS.2008.4674955

A 2GHz 65nm CMOS digitally-tuned BAW oscillator

Pierre Guillot ¹ Pascal Philippe ¹ Corinne Berland ² Jean-François Bercher ^{3, 2}

1 NXP Semiconductors

2 ESYCOM - Electronique, Systèmes de communication et Microsystèmes

3 LIGM - Laboratoire d'Informatique Gaspard-Monge

Abstract : The design of a 2GHz reference frequency oscillator in a 65nm CMOS process using a Bulk Acoustic Wave resonator is presented. The oscillator implements digital frequency control using a switched capacitor bank in parallel to the resonator. The tuning range is up to 4MHz with a minimum step of 1.6kHz. The oscillator core is designed to reach low phase noise (-128dBc/Hz at 100kHz offset) at low power consumption (0.9mW) using a differential topology. It is followed by a low noise divider for output at 500MHz with a phase noise of -140dBc/Hz at 100kHz offset.

Document type :

Conference papers

Domain :

Computer Science [cs] / Computation and Language [cs.CL]

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https://hal-upec-upem.archives-ouvertes.fr/hal-00621923
Contributor : Jean-François Bercher <>
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A 2GHz 65nm CMOS digitally-tuned BAW oscillator

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