A 2GHz 65nm CMOS digitally-tuned BAW oscillator

Pierre Guillot 1 Pascal Philippe 1 Corinne Berland 2 Jean-François Bercher 3, 2
1 NXP Semiconductors
2 ESYCOM - Electronique, Systèmes de communication et Microsystèmes
3 LIGM - Laboratoire d'Informatique Gaspard-Monge
Abstract : The design of a 2GHz reference frequency oscillator in a 65nm CMOS process using a Bulk Acoustic Wave resonator is presented. The oscillator implements digital frequency control using a switched capacitor bank in parallel to the resonator. The tuning range is up to 4MHz with a minimum step of 1.6kHz. The oscillator core is designed to reach low phase noise (-128dBc/Hz at 100kHz offset) at low power consumption (0.9mW) using a differential topology. It is followed by a low noise divider for output at 500MHz with a phase noise of -140dBc/Hz at 100kHz offset.
Type de document :
Communication dans un congrès
15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), Aug 2008, St. Julian's, Malta. IEEE, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, pp.722-725, 2008, 〈10.1109/ICECS.2008.4674955〉
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Dernière modification le : jeudi 12 juillet 2018 - 12:22:04
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Pierre Guillot, Pascal Philippe, Corinne Berland, Jean-François Bercher. A 2GHz 65nm CMOS digitally-tuned BAW oscillator. 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), Aug 2008, St. Julian's, Malta. IEEE, Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, pp.722-725, 2008, 〈10.1109/ICECS.2008.4674955〉. 〈hal-00621923〉

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