A 2GHz 65nm CMOS digitally-tuned BAW oscillator

Pierre Guillot 1 Pascal Philippe 1 Corinne Berland 2 Jean-François Bercher 3, 2
1 NXP Semiconductors
2 ESYCOM - Electronique, Systèmes de communication et Microsystèmes
3 LIGM - Laboratoire d'Informatique Gaspard-Monge
Abstract : The design of a 2GHz reference frequency oscillator in a 65nm CMOS process using a Bulk Acoustic Wave resonator is presented. The oscillator implements digital frequency control using a switched capacitor bank in parallel to the resonator. The tuning range is up to 4MHz with a minimum step of 1.6kHz. The oscillator core is designed to reach low phase noise (-128dBc/Hz at 100kHz offset) at low power consumption (0.9mW) using a differential topology. It is followed by a low noise divider for output at 500MHz with a phase noise of -140dBc/Hz at 100kHz offset.
Document type :
Conference papers
Complete list of metadatas

Cited literature [7 references]  Display  Hide  Download
https://hal-upec-upem.archives-ouvertes.fr/hal-00621923
Contributor : Jean-François Bercher <>
Submitted on : Thursday, March 17, 2016 - 12:21:34 PM
Last modification on : Thursday, February 7, 2019 - 2:21:21 PM
Long-term archiving on : Saturday, June 18, 2016 - 5:54:19 PM

File

ICECS_final_PG2008.pdf
Files produced by the author(s)

Identifiers

Collections

UPEC-UPEM | LIGM | LIGM_SIGNAL | ENPC | PARISTECH | ESYCOM | ESIEE-PARIS

Citation

Pierre Guillot, Pascal Philippe, Corinne Berland, Jean-François Bercher. A 2GHz 65nm CMOS digitally-tuned BAW oscillator. 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), Aug 2008, St. Julian's, Malta. pp.722-725, ⟨10.1109/ICECS.2008.4674955⟩. ⟨hal-00621923⟩

Export

BibTeX TEI DC DCterms EndNote

Share

Metrics

Record views

391

Files downloads

252

Contact

support.ccsd.cnrs.fr
hal.support@ccsd.cnrs.fr
Logo CCSD