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A 2GHz 65nm CMOS digitally-tuned BAW oscillator
Abstract : The design of a 2GHz reference frequency oscillator in a 65nm CMOS process using a Bulk Acoustic Wave resonator is presented. The oscillator implements digital frequency control using a switched capacitor bank in parallel to the resonator. The tuning range is up to 4MHz with a minimum step of 1.6kHz. The oscillator core is designed to reach low phase noise (-128dBc/Hz at 100kHz offset) at low power consumption (0.9mW) using a differential topology. It is followed by a low noise divider for output at 500MHz with a phase noise of -140dBc/Hz at 100kHz offset.
Cited literature [7 references]
https://hal-upec-upem.archives-ouvertes.fr/hal-00621923
Contributor : Jean-François Bercher <>
Submitted on : Thursday, March 17, 2016 - 12:21:34 PM
Last modification on : Wednesday, February 26, 2020 - 7:06:08 PM
Document(s) archivé(s) le : Saturday, June 18, 2016 - 5:54:19 PM
Contributor : Jean-François Bercher <>
Submitted on : Thursday, March 17, 2016 - 12:21:34 PM
Last modification on : Wednesday, February 26, 2020 - 7:06:08 PM
Document(s) archivé(s) le : Saturday, June 18, 2016 - 5:54:19 PM
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ICECS_final_PG2008.pdf
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